PPPL scientist uncovers physics behind plasma-etching process

Physicist Igor Kaganovich at the Department of Energy's (DOE) Princeton Plasma Physics Laboratory (PPPL) and collaborators have uncovered some of the physics that make possible the etching of silicon computer chips, which power cell phones, computers, and a huge range of electronic devices.

Specifically, the team found how electrically charged gas known as plasma makes the etching process more effective than it would otherwise be. The research, published in two papers appearing in the September and December 2016 issues of Physics of Plasmas, was supported by the DOE's Office of Science (FES).

Kaganovich, Deputy Head of the PPPL Theory Department, together with Dmytro Sydorenko of the University of Alberta, knew that the plasma etching process was effective, but were not sure exactly how the process worked. So they investigated the process's theoretical underpinnings.

During the etching process, a piece of silicon is placed in a chamber and immersed within a thin layer of plasma, about two centimeters wide. Also within the plasma are two electrodes spaced a couple of centimeters apart that produce a beam of electrons. As the electrons flow through the plasma, they start a process known as a two-stream instability, which excites plasma waves that enable the plasma to etch the silicon more efficiently.

Sydorenko and Kaganovich modeled this process. They showed that the waves created by the electron beam can become much more intense than in plasmas that are not bounded by electrodes.

In other words, when a plasma is bounded, the wave driven by the two-stream instability can become very strong. "The simulations indicate that the placing of plasma within a pair of electrodes supports the excitation of large plasma waves, which then lead to the acceleration of plasma electrons that can aid etching," Kaganovich said.

Understanding the physics undergirding the plasma etching technique could help researchers design more efficient processes to etch circuits on silicon chips.